View AFBR-5978Z_9055918.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

AFBR-5978Z digital diagnostic 650nm transceiver for fast ethernet (10/100 mbps) with sc-rj connector data sheet features ? compatible with electrical and optical performance of the pofac recommendations for the fast ethernet over plastic optical fiber (pof). ? compatible with the electrical and optical perfor - mance of the profnet recommendations the fast ethernet over pof and hard-clad silica fiber (hcs). ? manufactured in an iso 9001 certifed facility ? dmi [digital diagnostics monitoring interface, sff-8472 rev 9.3], provides real-time monitoring of: - temperature - supply voltage - received optical power (alarm/warning fag) ? lvpecl signal detect output ? temperature range C25 to +85 c applications ? factory automation at fast ethernet speeds ? fast ethernet networking over pof and hcs ? link distance up to 50 m pof or 100 m hcs (see application note 5290 for details) hcs? is a trademark of ofs corporation AFBR-5978Z is compatible with the sc-rj connecting system from reichle & de-massari ag, switzerland description the AFBR-5978Z transceiver provides the system de - signer with the ability to implement fast ethernet (100 mbps) or ethernet (10 mbps) over 50 meter standard bandwidth 0.50.05 na pof and 100 meter standard bandwidth 0.370.04 na hcs fber. the connectivity available for the transceiver is sc-rj. this product is lead free and compliant with rohs. transmitter the transmitter contains a 650nm led with an integrat - ed driver. the led driver operates at 3.3 v. it receives a lvpecl compatible electrical input, and converts it into a modulated current driving the led. the led is pack - aged in an optical subassembly, part of the transmitter section. the optical subassembly couples the output optical power efciently into pof or hcs fber. receiver the receiver utilizes a si pin photodiode. the pin pho - todiode is packaged in an optical sub-assembly, part of the receiver section. this optical subassembly couples the optical power efciently from pof or hcs fber to the receiving pin. the integrated ic operates at 3.3 v and converts the photocurrent into lvpecl compatible elec - trical output. package the transceiver package consist of four basic elements; two optical subassemblies, an electrical subassembly and the housing as illustrated in the block diagrams in figure 1. the package outline drawing and pin out are shown in figures 2 and 3. patent - www.avagotech.com/patents
2 block diagram figure 1. block diagram data out signal detect out data in electrical subassembly quantizer ic driver ic top view pin photodiode sc-rj receptacle optical subassemblies led preamp ic differential single-ended differential dmi figure 2. package outline drawing. the optical subassemblies utilize a high volume assem - bly process together with low cost lens elements which result in a cost efective building block. the electrical subassembly consists of a high volume multilayer printed circuit board on which the ic chips and various surface mounted passive circuit elements are attached. the housing includes internal shields for the electri - cal and optical subassemblies to insure low emi emis - sions and high immunity to external emi felds. the outer housing including the duplex sc-rj connector is molded of flled non-conductive plastic to provide me - chanical strength and electrical isolation. the low profle of the avago technologies transceiver design complies with the maximum height allowed for the duplex sc-rj connector over the entire length of the package. the transceiver is attached to a printed circuit board with twelve signal pins and the two solder posts, which exit the bottom of the housing. the two solder posts provide the primary mechanical strength to withstand the mechanical loads imposed on the transceiver by mating with the sc-rj connectored fber cables. the solder posts are isolated from the circuit design of the transceiver and do not require connection to a ground plane on the circuit board
3 pin descriptions pin 1 sda: the data line of the two wire serial interface. this data line should be pulled up with a 4.7kC10k ? re - sistor on the host board to a supply of 3.3v 10%. pin 2 rx gnd: receiver ground pin. directly connect this pin to the receiver ground plane of the host board. pin 3 rx vcc: receiver power supply pin. provide +3.3 v dc via a receiver power supply flter circuit. locate the power supply flter circuit as close as possible to the vcc rx pin. pin 4 sd: signal detect pin. if an optical signal is present at the input of the receiver, sd output is a logic 1. absence of an optical signal to the receiver results in a logic 0 output. this signal detect output can be used to drive a lvpecl input on an upstream circuit, such as signal detect input or loss of signalCbar. proper lvpecl termination should be in place. see fgure 4. pin 5 rdata-: receiver data out bar. this data line is a 3.3v lvpecl compatible diferential line which should be properly terminated with a 130 ? pull up to vcc and 82 ? pull down to ground. pin 6 rdata+: receiver data out. this data line is a 3.3v lvpecl compatible diferential line which should be properly terminated with a 130 ? pull up to vcc and 82 ? pull down to ground. figure 3. pin out diagram pin 7 tx vcc: transmitter power supply. provide +3.3v dc via a transmitter power supply flter circuit. locate the power supply flter circuit as close as possible to the vcc tx pin. pin 8 tx gnd: transmitter ground. directly connect this pin to the transmitter ground plane on the host board. pin 9 txdis: transmitter disable input. this input is used to shut down the transmitter light output. it is internally pulled up with a ~8 k ? resistor. low (0-0.8 v) - transmitter on between (0.8-2.0 v) - undefned high (2.0-3.63 v) C transmitter of open C transmitter of pin 10 tdata+: transmitter data in. this data line is an ac coupled 100 ? diferential line which does not need any termination at the user serdes. the ac coupling is done inside the module and therefore not required on the host board. pin 11 tdata-: transmitter data in bar. this data line is an ac coupled 100 ? diferential line which does not need any termination at the user serdes. the ac coupling is done inside the module and therefore not required on the host board. pin 12 scl: the clock line of the two wire serial interface. this data line should be pulled up with a 4.7k C 10 k ? resistor on the host board to a supply of 3.3v 10%. sda rxgnd rxvcc sd rdata- rdata+ scl tdata- tdata+ txdis txgnd txvcc bottom view sc-rj connector
4 figure 4. recommended termination circuit. pc master AFBR-5978Z protocol ic & serdes led driver amplifier & tx disable td+ td- rd+ rd- signal detect txdis tdata+ txvcc tdata- rd at a+ rd at a- sd sda scl eeprom 100 10nf 10nf 130 130 82 82 4.7k -10k 4.7k -10k v cc 3.3v 82 130 1 h 1 h 10 f 0.1 f 0.1 f v cc 3.3 v 1 0 f 0.1 f v cc 3.3 v v cc 3.3 v z = 50 z = 50 z = 50 z = 50 rx v cc quantisizer board layout C decoupling circuit and ground planes it is important to take care in the layout of your circuit board to achieve optimum performance from the trans - ceiver. a power supply decoupling circuit is recom - mended to flter out noise to assure optimal product performance. it is further recommended that a contigu - ous ground plane be provided in the circuit board di - rectly under the transceiver to provide a low inductance ground for signal return current. this recommendation is in keeping with good high frequency board layout practices. functional data i/o the lvpecl receiver output of the avago technologies transceiver can be dc-coupled to the lvpecl compli - ant network interface through a thvenin equivalent transformation. for a 3.3v power supply the lvpecl outputs should be pulled up to vcc with a 130 ? resistor and pulled down to ground with an 82 ? resistor. both coupling resistors are preferably placed close to the network interface ic, see fgure 4. ac-coupling can be used for systems in which the transceiver and connected logic are at diferent supply voltages. for ac coupling, the coupling capacitor should be large enough to avoid excessive low-frequency droop when the data signal contains long strings of consecutive identical digits. the lvpecl outputs have to be pulled down to ground frst to dc bias the output before ac coupling. because the lvpecl output common-mode voltage is fxed at vcc C 1.3v, the dc-biasing resistor can be selected by as - suming 14 ma dc current. this results in a bias-resistor value of 142 ? - 200 ? . after the ac-coupling capacitors, a thvenin equivalent transformation connects to the lvpecl compatible network interface, equal to the one used in dc-coupling.
5 figure 5. digital diagnostic memory map C specifc data feld description (from sff-8472 msa) the diagnostic monitoring interface (dmi) has two 256 byte memory maps in eeprom which are accessible over a two wire interface: the serial id memory map at address 1010000x (0xa0) and the digital diagnostic memory map at address 1010001x (0xa2). the serial id memory map contains a serial identifca - tion and vendor specifc information and is read only. the digital diagnostic memory map contains device operating parameters and alarm and warning fags. the operating parameters are to be retrieved through a se - quential read command ensuring that the msb and lsb of each parameter are coherent. furthermore, it con - tains 120 bytes that can be written by the user as well as a writable soft control byte. tables 1 to 6 detail memory contents, timing character - istics, soft commands and alarm/warning fags. digital diagnostics monitoring interface the AFBR-5978Z transceiver features an enhanced digital diagnostic interface, compliant to the digital di - agnostic monitoring interface for optical transceivers sff-8472 multi-source agreement (msa). please refer to the msa document to access information on the range of options, both hardware and software, available to the host system for exploiting the available digital diagnos - tic features. the enhanced digital interface allows real-time access to device operating parameters, and includes optional digital features such as soft control and monitoring of i/o signals. in addition, it fully incorporates the func - tionality needed to implement digital alarms and warn - ings, as defned by the sff-8472 msa. with the digital diagnostic monitoring interface, the user has capability of performing component monitoring, fault isolation and failure prediction in their transceiver-based applica - tions. 2 wire address 1010000x (a0h) 2 wire address 1010001x (a2h) 0 95 127 255 serial id dened by sfp msa (96 bytes) vendor specic (32 bytes) reserved in sfp msa (128 bytes) 0 55 alarm and warning thresholds (56 bytes) cal constants (40 bytes) 119 time diagnostic interface (24 bytes) 247 user writable eeprom (120 bytes) vendor specic (8 bytes) 255 127 vendor specic (8 bytes)
6 table 1. transceiver soft diagnostics timing characteristics parameter symbol min max unit notes hardware tx_disable assert time t_of 10 s note 1, figure 6 hardware tx_disable negate time t_on 1 ms note 2, figure 6 time to initialize t_init 100 ms note 3, figure 6 hardware rx_sd assert time t_sd_on 100 s note 4 hardware rx_sd de-assert time t_sd_of 100 s note 5 software tx_disable assert time t_of_soft 100 ms note 6 software tx_disable negate time t_on_soft 100 ms note 7 software rx_sd assert time t_sd_on_soft 100 ms note 8 software rx_sd de-assert time t_sd_of_soft 100 ms note 9 analog parameter data ready t_data 1000 ms note 10 serial bus hardware ready t_serial 300 ms note 11 write cycle time t_write 10 ms note 12 serial id clock rate f_serial_clock 400 khz note 13 notes: 1. time from rising edge of tx_disable to when the optical output falls below 10% of nominal. 2. time from falling edge of tx_disable to when the modulated optical output rises above 90% of nominal. 3. time from power on or falling edge of tx_disable to when the modulated optical output rises above 90% of nominal. 4. time from valid optical signal to rx_sd assertion. 5. time from loss of optical signal to rx_sd de-assertion. 6. time from two-wire interface assertion of tx_disable (a2h, byte 110, bit 6) to when the optical output falls below 10% of nominal. measured from falling clock edge after stop bit of write transaction. 7. time from two-wire interface de-assertion of tx_disable (a2h, byte110, bit 6) to when the modulated optical output rises above 90% of nominal. 8. time for two-wire interface assertion of rx_sd (a2h, byte 110, bit 1) from presence of valid optical signal. 9. time for two-wire interface de-assertion of rx_sd (a2h, byte 110, bit 1) from loss of optical signal. 10. from power on to data ready bit asserted (a2h, byte 110, bit 0). data ready indicates analog monitoring circuitry is operational. 11. time from power on until module is ready for data transmission over the serial bus (reads or writes over a0h and a2h). 12. time from stop bit to completion of a 1-8 byte write command. 13. contact avago technologies for applications at faster (>400 khz) serial id clock rates.
7 figure 6. transceiver timing diagrams. table 2. transceiver digital diagnostic monitor characteristics parameter symbol min. unit notes transceiver internal temperature accuracy t int 5.0 c temperature is measured internal to the transceiver. valid from -25c to 85c case temperature. transceiver internal supply voltage accuracy v int 0.1 v supply voltage is measured internal to the transceiver and can, with less accuracy, be correlated to voltage at the vcc pin. valid over 3.3v 10%. mechanical dimension - dust cap mechanical dimensions in millimeters front right bottom iso 23.3 12.8 3 6.1 14.35 8.5 11.35 9 v cc > 2.97 v t x _di s abl e tr a n s m itte d signa l t_ init t-init: tx_disable negated v cc > 2.97 v t x _di s abl e tr a n s m itte d signa l t_ init t-init: tx_disable asserted optical signal sd t_sd_on t_sd_o tx-sd-on & tx-sd-o occurrence of loss t x _di s abl e tr a n s m itte d signa l t_o t_on t-o & t-on: tx disable asserted then negated
8 table 3. eeprom serial id memory contents C address a0h addr hex ascii description addr hex ascii description 0 00 40 41 a 1 00 41 46 f 2 00 42 42 b 3 00 43 52 r 4 00 44 2d - 5 00 45 35 5 6 00 46 39 9 7 00 47 37 7 8 00 48 38 8 9 00 49 5a z 10 00 50 20 11 00 51 20 12 00 52 20 13 00 53 20 14 00 54 20 15 00 55 20 16 00 56 20 17 00 57 20 18 00 58 20 19 00 59 20 20 41 a 60 02 note 1 21 56 v 61 8a note 1 22 41 a 62 00 note 1 23 47 g 63 note 4 24 4f o 64 00 25 20 65 14 26 54 t 66 00 27 45 e 67 00 28 43 c 68 - 83 note 2 29 48 h 84 - 91 note 3 30 20 92 68 h 31 20 93 d0 32 20 94 01 33 20 95 note 4 34 20 96 - 127 note 5 35 20 36 00 37 00 38 17 39 6a notes: 1. led wavelength is represented in 16 unsigned bits. the hex representation of 650 (nm) is 0x28a. 2. address 68-83 specify a unique module serial number. 3. address 84-91 specify the date code. 4. address 63 is the checksum for bytes 0-62 and address 95 is the checksum for bytes 64-94. they are calculated (per sff-8472) and stored prior to product shipment. 5. address 96-127 is vendor specifc.
9 table 4. eeprom dmi memory contents C address a2h addr hex dec description addr hex dec description 0 73 115 temp h alarm msb [1,5] 95 checksum for bytes 0 to 94 [7] 1 00 0 temp h alarm lsb [1,5] 96 real time temperature msb [1] 2 d8 216 temp l alarm msb [1,5] 97 real time temperature lsb [1] 3 00 0 temp l alarm lsb [1,5] 98 real time vcc msb [2] 4 69 105 temp h warning msb [1,5] 99 real time vcc lsb [2] 5 00 0 temp h warning lsb [1,5] 100 to 109 reserved [8] 6 e7 231 temp l warning msb [1,5] 110 status control - see table 5 7 00 0 temp l warning lsb [1,5] 111 reserved [8] 8 98 152 vcc h alarm msb [2,5] 112 flag bit - see table 6 9 58 88 vcc h alarm lsb [2,5] 113 flag bit - see table 6 10 69 105 vcc l alarm msb [2,5] 114 reserved [8] 11 78 120 vcc l alarm lsb [2,5] 115 reserved [8] 12 8d 141 vcc h warning msb [2,5] 116 flag bit - see table 6 13 cc 204 vcc h warning lsb [2,5] 117 flag bit - see table 6 14 74 116 vcc l warning msb [2,5] 118 reserved [8] 15 04 4 vcc l warning lsb [2,5] 119 to 127 vendor specifc 16 to 39 reserved [8] 128 to 247 customer writable 40 08 8 rx oma margin l alarm [3,4,5] 248 to 255 vendor specifc 41 12 18 rx oma margin l warning [3,4,5] 42 to 55 reserved [8] notes: 1. temperature (temp) is decoded as a 16 bit signed twos complement integer in increments of 1/256 c. 2. supply voltage (vcc) is decoded as a 16 bit unsigned integer in increments of 100 v. 3. received optical modulation amplitude margin or rx oma margin is a measure for the reserve in oma to sensitivity. 4. received oma margin is decoded as an 8 bit signed twos compliment integer in increments of 0.2 db. 5. this register is read only. a write will be acknowledged but not stored. 6. bytes 56-94 are not intended for use with AFBR-5978Z, but have been set to default values per sff-8472. 7. byte 95 is a checksum calculated (per sff-8472) and stored prior to product shipment. 8. reserved registers will return 00 when read. a write to a reserved register will be acknowledged but not stored.
10 table 5. eeprom serial id memory contents C soft commands (address a2h, byte 110) bit # status / control name description notes 7 tx_disable state digital state of tx_disable input pin (logic 1 = tx_disable asserted) note 1 6 soft tx_disable read/write bit for changing digital state of tx_disable function note 1,2 5 reserved note 3 4 not supported note 4 3 not supported note 5 2 not supported note 6 1 rx_sd state digital state of the rx_sd output pin (logic 0 = rx_sd asserted) note 1 0 data ready (bar) indicates transceiver is powered and real time sense data is ready(0 = ready) note 7 notes: 1. the response time for soft commands of the AFBR-5978Z is 100 ms as specifed by the msa sff-8472. 2. bit 6 is logic ord with the tx_disabled input pin. either asserted will disable the transmitter. 3. reserved bits will return 0 when read. a write to a reserved bit will be acknowledged but not stored. 4. a read from bit 4 will return 1. a write will be acknowledged but not stored. 5. a read/write from/to bit 3 will be acknowledged and stored but will be ignored by the transceiver. 6. a read from bit 2 will return 0. a write will be acknowledged but not stored. 7. AFBR-5978Z meets the msa sff-8471 data ready timing of 1000 ms. table 6. eeprom serial id memory contents C alarm and warnings (address a2h, bytes 112, 113, 116, 117) byte bit flag bit name description 112 7 temp high alarm set when transceiver internal temperature exceeds high alarm threshold 6 temp low alarm set when transceiver internal temperature exceeds low alarm threshold 5 vcc high alarm set when transceiver internal supply voltage exceeds high alarm threshold 4 vcc low alarm set when transceiver internal supply voltage exceeds low alarm threshold 3-0 reserved note 1 113 7-6 reserved note 1 5 rx oma margin low alarm set when received rx oma margin exceeds low alarm threshold, note 2 4-0 reserved note 1 116 7 temp high warning set when transceiver internal temperature exceeds high warning threshold 6 temp low warning set when transceiver internal temperature exceeds low warning threshold 5 vcc high warning set when transceiver internal supply voltage exceeds high warning threshold 4 vcc low warning set when transceiver internal supply voltage exceeds low warning threshold 3-0 reserved note 1 117 7-6 reserved note 1 5 rx oma margin low warning set when receiver rx oma margin exceeds low warning threshold, note 2 4-0 reserved note 1 notes: 1. reserved bits will return 0 when read. a write to a reserved bit will be acknowledged but not stored. 2. received optical modulation amplitude margin or rx oma margin is a measure for the reserve in oma to sensitivity.
11 absolute maximum ratings stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. limits apply to each parameter in isolation, all other parameters having values within the recommended operation conditions. it should not be assumed that limiting values of more than one parameter can be applied to the products at the same time. exposure to the absolute maximum ratings for extended periods can adversely afect device reliability. parameter symbol min max unit notes storage temperature t s -40 +100 c case operating temperature t c -25 +85 c lead soldering temperature t sold 260 c note 1 lead soldering time t sold 10 s note 1 supply voltage v cc -0.5 4.0 v data input voltage v i -0.5 v cc v diferential input voltage v d 2.0 v peak to peak output current pecl i dout -50 50 ma esd-resistance - human body model v esd -2 +2 kv note 2 esd-resistance - air discharge v esd -8 +8 kv note 3 esd-resistance - contact discharge v esd -6 +6 kv note 4 electric field immunity v emi 15 v/m iec 61000-4-3 notes: 1. the transceiver is pb-free wave solderable. 2. human body model: 100pf/1.5k ? , 5 pulse / polarity; mil-std.883 meth. 3015. 3. air discharge iec 61000-4-2 level 3 esd-resistance for the transceiver. 4. contact discharge iec 61000-4-2 level 3 esd resistance for the transceiver. regulatory compliance table feature test method performance mil-std 883 method 3015, 100 pf / 1.5 k 5 pulse per polarity esd resistance human body model 2 kv iec 61000-4-2 typically withstand an electrostatic discharge without dam - age when the sc-rj connector receptacle is contacted by a human body model probe level 3air discharge esd resistance 8 kv contact discharge esd resistance 6 kv iec 61000-4-3 typically show no measurable efect from an electric feld applied to the transceiver when mounted to a circuit board without chassis enclosure. level 3 10 v/m electric feld immunity: en60825-1 as specifed in iec 60825-1 version 1.2. ael class 1 tv certifcate number r72062581
12 recommended operating conditions parameter symbol min typ max unit notes case operating temperature t c -25 +85 c supply voltage v cc 2.97 3.3 3.63 v diferential input voltage v d 0.4 0.800 1.6 v peak to peak data and signal detect output load r l 50 ? signalling rate (fast-ethernet) b 125 mbd 4b/5b, 5 signalling rate (ethernet) b 20 mbd manchester, 5 humidity 5 95 % notes: 5. ethernet and fast ethernet optical auto-negotiation signals over a 1 mhz carrier are supported. transceiver electrical characteristics parameter symbol min typ max unit notes supply current i cc 250 300 ma power dissipation p diss 825 mw power supply noise reduction psni 50 mv peak to peak transmitter electrical characteristics parameter symbol min typ max unit notes data in current - low i din -2 m a data in current - high i din 18 m a
13 notes: 6. measured at the end of 1 meter optical fber. 7. central wavelength is defned as: ref: eia/tia standard fotp-127/6.1, 1991 8. spectrum rms is defned as: ref: eia/tia standard fotp-127/6.3, 1991 transmitter optical characteristics parameter symbol min typ max unit notes average launched power (1mm pof, na=0.5) po -8.5 -4.5 -2 dbm note 6 average launched power (200um hcs, na=0.37) po -19.5 -15 -11 dbm note 6 optical modulation amplitude (pof) oma -6.5 -3 -0.5 dbm peak to peak, note 6 optical modulation amplitude (hcs) oma -17.5 -13.5 -9.5 dbm peak to peak, note 6 central wavelength l c 635 650 660 nm note 6, 7 spectrum rms dl 17 nm note 6, 8 optical rise time (10%-90%) t r 2.7 6.5 ns note 6 optical fall time (10%-90%) t f 2.7 6.5 ns note 6 duty cycle distortion contributed by the transmit - ter dcd -1 +1 ns peak to peak, note 6 random jitter contributed by the transmitter rj 0.2 ns peak to peak, note 6 overshoot ov 40 % note 6 = = = n i i n i i i p p c 1 1 2 1 1 1 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? = = c p p n i i n i i i
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2013 avago technologies. all rights reserved. obsoletes av01-0507en av02-1505en - january 28, 2013 receiver electrical characteristics parameter symbol min typ max unit notes data output voltage - low v ol -v cc -1.63 v data output voltage - high v oh -v cc -0.99 v data output voltage swing |v oh -v ol | 400 800 mv single ended data output rise time t r 1.45 2.20 ns data output fall time t f 0.98 2.20 ns duty cycle distortion dcd -1 +1 ns peak to peak data dependent jitter (rise/fall) ddj 0.6 1.5 ns peak to peak random jitter rj 0.1 0.2 ns peak to peak signal detect output voltage - low v ol -v cc -2.2 -1.63 -1.5 v signal detect output voltage - high v oh -v cc -1.2 -0.99 -0.7 v receiver optical characteristics parameter symbol min typ max unit notes unstressed receiver sensitivity, oma (pof) oma -22.5 -25 dbm peak-peak, note 9 unstressed receiver sensitivity, oma (hcs) oma -26.3 -29.3 dbm peak-peak, note 9 input optical power maximum, oma (pof) p in max +1 dbm peak-peak, note 10 input optical power maximum, oma (hcs) p in max -4 dbm peak-peak, note 10 operating wavelength r 635 650 660 nm signal detect asserted p a 2 db note 11 signal detect de-asserted p d 5 db note 11 signal detect hysteresis p a - p d 1.5 3 db notes: 9. measured with prbs 2 7 -1 sequence, ber < 2.5x10 -10 . 10. input optical power maximum is defned as the maximum optical modulation amplitude where the receiver duty cycle distortion reaches 1 ns. 11. signal detect asserted and de-asserted levels are indicated as db below unstressed receiver sensitivity level for either pof or hcs.

▲Up To Search▲

Price & Availability of AFBR-5978Z

	To Download AFBR-5978Z Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .